1. Field of the Invention
The present invention relates to integrated circuits, and in particular relates to using programmable logic devices to emulate logic circuits.
2. Discussion of Related Art
In developing an integrated circuit ("target logic circuit") it is often necessary to provide an implementation of the design in a development system prior to committing the design to a final implementation, such as an ASIC (application specific integrated circuit) or a custom integrated circuit design. Such implementation in a development system is used not only for debugging the integrated circuit, but also for developing systems ("target systems") which will use the integrated circuit. Two methods for providing an implementation of the design at the development stage are software simulation and hardware emulation.
Software simulation of electronic circuit designs has become an important tool for designers. Simulation allows a design to be validated without using a hardware implementation. However, software simulation are limited in at least three aspects. Firstly, compared to the actual operating speed of the target logic circuit, software simulation is slow. Secondly, constructing simulation models is required to capture certain operating characteristics of the target logic circuit, such as circuit delay. Lastly, where some part of a design has been implemented in hardware, it is virtually impossible, although desirable, to use software simulation to connect software simulated parts of the circuit to the implemented hardware so as to provide a simulation of the total design.
Alternatively, a class of hardware simulators, called "VLSI emulators", can be used to achieve near real time in-circuit emulation. VLSI emulators converts a logic circuit design description or representation into a temporary operating hardware form ("emulation circuit") using reprogrammable logic devices, such as an array of interconnected field programmable gate arrays. Even then, there are several limitations of today's emulation technology.
A first disadvantage of the prior art is an error condition known as "hold time violation artifact". Hold time violation artifact is an error condition arising in an emulation circuit having relatively complex clocking structure. This error condition results from the fact that clock skews in the emulation circuit are frequently different from the clock skews of the target logic circuit, because limited resources in reprogrammable logic devices are designed to support the generation and routing of clock signals. Thus, since the error condition is an artifact of the emulation circuit, hold time violation may not actually occur in the target logic circuit. Because today's designs are large and often requiring complex clocking schemes, hold time violation artifact can be expected to occur in all but very simple emulation circuits.
A practical VLSI emulator is required to take a large design, partitions such a design to implement the circuit over hundreds of field programmable gate arrays, and then interconnects these field programmable gate array to arrive at a functional emulation circuit. Because an effective strategy is lacking in the prior art for partitioning components of the target logic circuit to minimize interconnection delays and interchip connections, another disadvantage of the prior art is the unsatisfactory circuit performance (i.e. speed) of the emulation circuit, due to avoidable delays of both long interconnection paths within a programmable logic device and interchip interconnections.
A third disadvantage of the prior art is the low utilization efficiency of programmable logic devices. Such low utilization efficiency arises because the numerous interconnections between field programmable gate arrays quickly use up the available I/O pins before a high percentage of the available gates are utilized.
U.S. Pat. No. 5,036,473 to M. Butts et al., entitled "Method of Using Electronically Reconfigurable Logic Circuits", filed Oct. 4, 1989, issued Jul. 30, 1991, describes a method using a number of reprogrammable gate array logic chip to implement a logic circuit.
Similarly, European Patent Application entitled "Apparatus for Emulation of Electronic Hardware System," by S. Sample et al, discloses configurating an array of programmable logic arrays to provide an emulation circuit.
However, neither Butts et al. nor Sample et al. addresses the problems of hold time violation artifact, and utilization and delay optimizations. Thus, for any design of practical size and complexity, the methods of Butts et al. and Sample et al achieve a functional circuit only after considerable manual debugging.